1. Field of the Invention
The present invention relates to the structure of a static semiconductor memory and, more particularly, to the structure of a static semiconductor memory which is capable of accomplishing a high-speed low-power-consumption operation on a low power supply voltage.
2. Description of the Background Art
A conventional static semiconductor memory is described below using as an example a static random access memory (referred to hereinafter as an SRAM). FIG. 20 is a schematic block diagram of reading system circuitry of a conventional SRAM 3000. The reading system circuitry of the conventional SRAM 3000 comprises a memory cell 3004; bit lines BL and /BL connected to the memory cell 3004; constant current sources 3006a and 3006b for supplying predetermined constant currents to the bit lines BL and /BL, respectively; a precharge circuit 3002 for precharging the bit lines BL and /BL up to an internal power supply potential prior to the start of a read operation; and a read circuit 3008 receiving the potentials of the bit lines BL and /BL to output read data. The read data having complementary values are provided to the bit lines BL and /BL.
The memory cell 3004 comprises a static latch circuit including a pair of inverters 3010 and 3012 which are inverse-parallel connected between a pair of storage nodes N1 and N2, the bit lines BL and /BL, and a pair of access transistors 3014 and 3016 for making and breaking connection with the storage nodes N1 and N2 in response to a potential level of a word line WL.
FIG. 21 is a detailed circuit diagram of the memory cell 3004 shown in FIG. 20. The inverter 3010 includes a high resistance element R2 and a driver transistor Q2 which are connected in series between a potential point at a power supply potential VCC and a potential point at a ground potential GND. The inverter 3012 includes a high resistance element R1 and a driver transistor Q1 which are connected in series between a potential point at the power supply potential VCC and a potential point at the ground potential GND. For implementation of the static latch circuit, connection is established between the gate of the driver transistor Q1 and the drain of the driver transistor Q2 (the storage node N2) and between the gate of the driver transistor Q2 and the drain of the driver transistor Q1 (the storage node N1).
Access transistors Q3 and Q4 correspond to the transistors 3014 and 3016 shown in FIG. 20, respectively. The access transistor Q3 is connected between the bit line BL and the storage node N1, and has a gate connected to the word line WL. The access transistor Q4 is connected between the bit line /BL and the storage node N2, and has a gate connected to the word line WL.
The driver transistors Q1 and Q2 and the access transistors Q3 and Q4 are N-channel MOS transistors, and the high resistance elements R1 and R2 are used as load elements for the memory cell. Such a memory cell is generally referred to as a high resistance load memory cell.
In general, the high resistance load memory cell has a multilevel structure for reduction in memory cell area. Specifically, the load elements (high resistance elements R1 and R2) of the high resistance load memory cell are formed of polysilicon in a level over the driver transistors Q1 and Q2 and access transistors Q3 and Q4 which are formed on a silicon substrate not shown, with an insulating layer therebetween.
FIG. 22 is a detailed circuit diagram of another form of the memory cell 3004. P-channel MOS transistors Q5 and Q6 are used as the load element for the memory cell in place of the high resistance elements R1 and R2 of the structure shown in FIG. 21. The gates of the P-channel MOS transistors Q5 and Q6 are connected to the gates of the driver transistors Q1 and Q2, respectively. Such a memory cell is generally referred to as a CMOS memory cell.
The P-channel MOS transistors Q5 and Q6 may be thin-film transistors, and are formed over the transistors Q1 to Q4, with an insulating layer therebetween, similar to the high resistance elements R1 and R2.
FIG. 23 is a graph showing the transfer characteristics of the memory cell 3004 shown in FIGS. 21 and 22 when the word line WL is in a selected state. The graph of FIG. 23 plots the potential at the storage node N1 versus the potential at the storage node N2 for the characteristics of the inverter 3012 (broken curve) and the inverter 3010 (solid curve). The power supply potential VCC is set to 3 V, for example. The fine line in the graph of FIG. 23 indicates the positions in which the potential at the node N1 equals the potential at the node N2.
In FIG. 23, points A1 and A2 are bistable points for the memory cell 3004. These two points A1 and A2 must exist in order to prevent damages to the data stored in the memory cell 3004 and to ensure the retention of the data. The two bistable points are ensured by sufficiently enlarging zones B1 and B2 (referred to hereinafter as "memory cell eyes") surrounded by the broken and solid curves indicative of the characteristics of the inverters 3012 and 3010. A memory cell eye is also referred to as a static noise margin. The gradients of curves C1 and C2 represent the magnitudes of the gains of the inverters 3010 and 3012, respectively. The steeper the gradients of the curves, the higher the gains of the inverters of the memory cell.
With the word line WL in the selected state, the access transistors Q3 and Q4 are on to cause the gains of the inverters 3012 and 3010 to be lower than those provided when the word line WL is in a non-selected state, reducing the area of the memory cell eyes B1 and B2. The reason therefor is that the stability of the memory cell 3004 is determined by the characteristics of a circuit including the in-series connected access transistor Q3 and driver transistor Q1 and a circuit including the in-series connected access transistor Q4 and driver transistor Q2.
For the memory cell eyes B1 and B2 large enough to ensure the retention of the data stored in the memory cell 3004, it is desirable that the transistor size of the driver transistors Q1 and Q2 is at least three times that of the access transistors Q3 and Q4. The transistor size may be defined as the ratio of a channel width W to a channel length L, for example.
In the background art semiconductor memory, it has been desirable to increase the area of the driver transistors for stability of the memory cell data as above described. This presents a first problem in that the reduction in the required area of the memory cell is hindered.
A second problem of the background art semiconductor memory is that it is difficult to decrease the power supply voltage required to stably operate the memory cell. FIG. 24 is a graph corresponding to the graph of FIG. 23 and showing the transfer characteristics of the memory cell, with the word line WL in the selected state, when the power supply potential VCC is set to 2 V. As illustrated in FIG. 24, the decrease in power supply voltage reduces the area of the memory cell eyes B1 and B2, which might cause the two bistable points A1 and A2 to disappear. This results in latch-up, failing to stably hold the memory cell data.
FIG. 25 is a schematic block diagram of another form of the reading system circuitry of the SRAM 3000 for ameliorating the second problem. The reading system circuitry of FIG. 25 comprises a P-channel cross-coupled load 3040 in place of the constant current sources 3006a and 3006b of the arrangement shown in FIG. 20. The P-channel cross-coupled load 3040 is used as a reading load circuit for the bit lines BL and /BL.
The precharge circuit 3002 precharges the bit lines BL and /BL up to "H" (e.g., the power supply potential VCC) before the data is read from the memory cell 3004. In the memory cell 3004, the storage node N1 adjacent the access transistor Q3 connected to the bit line BL stores "H", and the storage node N2 adjacent the access transistor Q4 connected to the bit line /BL stores "L".
The precharge is completed as the word line WL is selected, and the data stored in the memory cell 3004 is outputted to the bit lines BL and /BL. "H" is transmitted from the storage node N1 to the bit line BL, and "L" is transmitted from the storage node N2 to the bit line /BL.
A transistor 3042 of the P-channel MOS cross-coupled load 3040 turns on since the potential of the bit line /BL which is low is applied to the gate of the transistor 3042. This causes the potential of the bit line BL to be pulled up to the power supply potential VCC. On the other hand, a transistor 3044 of the P-channel MOS cross-coupled load 3040 turns off, and the potential of the bit line /BL which is not pulled up remains low. As above described, the rise in the potential level of the bit line which outputs "H" up to the power supply potential VCC is advantageous in implementation of a noise-resistant SRAM. An SRAM for improving an operating margin by the above described technique is disclosed in, for example, Japanese Patent Application Laid-Open No. 5-101676 (1993).
However, it is apparent from the above described operation that the P-channel MOS cross-coupled load transistors 3042 and 3044, similar to the P-channel MOS transistors Q5 and Q6 shown in FIG. 22, merely passively receive the amplitudes of the potentials of the bit lines BL and /BL to promote the changes in the potentials.
There is a likelihood of damages to the data held in the memory cell 3004 if the current value supplied from the cross-coupled load 3040 is excessively great relative to the current driving capability of the memory cell 3004. To avoid this, the current driving capability of the cross-coupled load transistors 3042 and 3044 must be set to a small value. However, setting the current driving capability to the small value creates a third problem in that it takes much time to charge and discharge the bit lines BL and /BL for reading data from the memory cell 3004, resulting in prolonged delay time required until the data reading is completed.